1. Field of the Invention
This invention relates to the field of state storage circuitry, including different types of latches, flip-flops, registers etc. More particularly, this invention relates to the control of such state storage circuitry with clock signals.
2. Description of the Prior Art
FIG. 1 of the accompanying drawings illustrates a known inverting mux-D scan flop built using CMOS circuitry. The functional data signal d is applied to a P-type gate and a N-type gate within a stack comprising three P-type gates and three N-type gates. This stack also includes two gates switched by the scan enable signal se and the complement of the scan enable signal nse. The final two transistors within the stack are switched by the complement nclk of the input clock clk to the clock tree illustrated as well as a buffered clock bclk generated from clock nclk. When scan enable is not asserted, the gates controlled by the scan enable signal se and the complement of the scan enable signal nse are conductive. Accordingly, the input data signal will pass through the six gate stack and be inverted when the clock nclk is high and the clock bclk is low. The time between the data signal being asserted and the rising edge of the input clock signal clk is the set up time of the flop. The signal which passes through the six transistor stack is captured in a master stage of the flop. During this capture the tristate invertor 2 is non-conductive. Once the clock nclk and the clock bclk transition, the data within the master stage will be held as the six transistor stack will be tristated. At this point, the tristate invertor 2 becomes conductive and the data captured within the master stage is transferred to the slave stage. When the input clock is returned to its original condition, the tristate invertor 2 will become non-conductive and the data within the slave stage will be held. When the data first enters the slave stage, it starts to drive the output q and this forms the end point of the clock to output delay.
Also shown in FIG. 1 are two P-type transistors with gates respectively controlled by the scan input signal si and the complement of the scan enable signal nse and two N-type transistors with gates respectively controlled by the scan input signal si and the scan enable signal se. These gates are used to insert scan data into the master stage of the flop. When scan enable is asserted, the data path for signal d is tristate and one of the sets of two transistors performing the scan data insertion will either pull the master stage up or pull the master stage down depending upon the scan input signal si providing the clock bclk is low and the clock nclk is high.
FIG. 2 illustrates a non-inverting mux-D scan flop of a design similar to that of FIG. 1. In particular the six gate stack and the scan inserting gates operate in the same manner.
A number of problems arise with the state storage circuitry illustrated in FIGS. 1 and 2. A first problem is that the functional data path into the latch is via a stack of six gates, namely three P-type gates and three N-type gates. This slows propagation of a data signal into the master stage. Furthermore, the same clocks that define the data set up time (i.e. the time at which the six gate stack will be tristate) are also used to control the clock to output delay time. Thus, whilst it may be desired to delay the time at which the six gate stack becomes tristated to permit a greater time for the master stage to properly capture the data value, this has a consequence of also increasing the clock to output delay.